Transient Safe Operating Area (tsoa) For Esd Applications

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identifie

Miscorrelation Between Air Gap Discharge And Human Metal Model Stresses Due To Multi-Finger Turn-On Effect

Operation of NLDMOS-SCR devices under the human metal model (HMM) and IEC air gap electrostatic discharge (ESD) stresses has been studied based on both the pulsed measurements and mixed-mode simulations. Under the IEC air gap testing, the devices are found to suffer the non-uniform multi-finger turn-on behavior and hence a relatively low passing level, whereas both the IEC contact and HMM stresses do not give rise to such an adversary effect and result in a considerably higher passing level. It is further shown that the non-uniform multi-finger turn-on effect depends on the stress pulse rise time. Such dependence has also been examined and verified using the transmission line pulsing (TLP) technique with rise times ranging from 10 to 40 ns

Analysis Of Safe Operating Area Of Nldmos And Pldmos Transistors Subject To Transient Stresses

Transient safe operating area (TSOA) of n-type and p-type laterally diffused metaloxidesemiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA. © 2006 IEEE

Nldmos Esd Scaling Under Human Metal Model For 40-V Mixed-Signal Applications

Electrostatic discharge (ESD) robustness of LDMOS (laterally diffused MOS) devices is found to be highly dependent on the type of ESD stress. In particular, the device\u27s ESD robustness does not scale with the device width, and this condition is substantially aggravated during the International Electrotechnical Commission (IEC) 61000-4-2 stress condition. IEC 61000-4-2 is a system-level ESD standard increasingly being adopted in the industry for ESD robustness assessment at the integrated circuit level. A comprehensive evaluation under the IEC 61000-4-2 stress impacting precision circuit designs is introduced in this letter for variable width LDMOS devices fabricated in a 0.18-μm bipolar-CMOS-DMOS process for 40-V mixed-signal applications. © 2012 IEEE

Bidirectional Devices For Automotive-Grade Electrostatic Discharge Applications

Color sequential projection display using a vertical field switching (VFS) polymer-stabilized blue phase liquid crystal (BPLC) is proposed. The VFS-BPLC exhibits submillisecond response time which is useful for suppressing color breakup. The proposed projector also has a small throw ratio. With phase compensation, the distortion from oblique LC panel could be corrected. © 2012 IEEE

Correlation Of Human Metal Model And Transmission Line Pulsing Testing

Passing voltage levels measured from the human metal model tester are correlated with the failure current levels obtained from the transmission line pulsing (TLP) tester for electrostatic discharge protection devices fabricated in 0.18-and 0.35-μm MOS technologies. Various relevant TLP parameters, including the holding voltage and on-state resistance, are accounted for in the improved correlation formula developed in this study. © 2011 IEEE

Transient Safe Operating Area (Tsoa) Definition For Esd Applications

The concept of Transient Safe Operating Area (TSOA) for electrostatic discharge (ESD) design is discussed in this paper. TSOA characterization is introduced to obtain ESD design targets and better synthesize protection-/core- devices actual transient over-voltage response for robust ESD performance in emerging high-voltage mixed-signal circuit applications. A first methodology based on the direct analysis of the transient response of output devices and clamps is demonstrated to achieve optimum protection of commonly sensitive high voltage output devices by either enabling self-protection or by combining the output device with a protection clamp. To extend the TSOA analysis and address the different problem of thin MOS gate oxide protection, a power-law based method is introduced to assess the TSOA and consistently provides effective input circuit protection. The TSOA is identified via fast transient measurements and ESD robustness is further evaluated in conjunction with protection devices. © 2009 ESDA

A New Esd Design Methodology For High Voltage Dmos Applications

A comprehensive methodology for synthesizing robust ESD performance in highly sensitive high voltage NLDMOS functional blocks is introduced. Optimizing high voltage output stage design for robust device- and system-level (IEC 61000-4-2)/HMM is assessed under 1-, 2-, 5-, 10- ,100-ns wide time frames of typical electrostatic discharge (ESD) stress models

Very Fast Transient Simulation And Measurement Methodology For Esd Technology Development

A Transient safe operating area (TSOA) definition for ESD applications is introduced. Within this concept framework, ESD protection device topologies developed in a mixed-signal submicron high-voltage CMOS technology are studied to identify turn-on voltage and the resulting voltage overshoot conditions during fast ESD transients. A state-of-the-art numerical simulation environment used to study and optimize the fast transient response of ESD protection devices is discussed and simulation results are benchmarked versus very fast transmission line pulsing measurements. Constraints for triggering control of clamp devices are also investigated via simulations and pulse measurements. ©2009 IEEE

A Review Of Core Compact Models For Undoped Double-Gate Soi Mosfets

In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed. © 2007 IEEE